Within the system verification phase of the V-model process.
Key contributions
- Configured test software pin bindings and expected-value checks from integration inputs, enabling automatic signal-anomaly detection on the host PC, with calibration and bus debugging on CANalyzer and RS582
- Performed hardware/software integration debugging of load-box test benches, identifying and resolving signal mapping errors, missing pull-up resistors, and missing driver microcode
- Led root-cause analysis of a severe radiated-emission failure on one programme: ran a 4M change analysis across supplier part swaps and assembly changes, then identified from the laboratory’s own recordings that the sample was cycling in immunity mode during an emissions scan. Directed a re-test in the correct mode, achieving a full-band pass with no board respin and no schedule slip
- Disproved a suspected ESD-damaged sample on a second programme by reproducing the identical fault on a backup unit flown to the laboratory, then localized the real cause from error codes and the condition sheet to load-board switches dislodged in transport, and resolved it remotely the same day
- Conducted EMC risk assessments for new programmes by benchmarking platform test reports against customer specifications, identifying test-parameter gaps and coverage blind spots, and reporting risk matrices to customers
- Travelled to a third-party laboratory to train its engineers on bench topology and on driving operating-mode changes from the host software
